Task and Memory Mapping Optimization for SDRAM Interference Minimization on Heterogeneous MPSoCs

Alfonso Mascareñas González (1) , Jean-Baptiste Chaudron (1) , Frédéric Boniol (2) , Youcef Bouchebaba (2) , Jean-Loup Bussenot (2)

1 ISAE-SUPAERO - Institut Supérieur de l'Aéronautique et de l'Espace
2 DTIS, ONERA, Université de Toulouse [Toulouse]

DDR SDRAM memories are resources commonly used on multicore platforms and hence, being a main source of interference. To deal with this issue, we propose a methodology based on task/memory mapping optimization through multi-objective heuristic-based algorithms. By placing the tasks on the platform cores and the memory in the DDR SDRAM banks, we minimize the DDR SDRAM interference while considering other aspects such as the task execution parallelism and deadline margin. To evaluate the fitness of the task/memory map, the optimization algorithms make use of cost function equations. In order to compute the DDR memory interference cost, we use a fast executing self-designed cost function. The execution parallelism is computed using the workload variance cost function. The deadline margin of a task is computed considering the inter and intra core interference. The task/memory mapping outcomes are checked through tests for which the heterogeneous MPSoCs Keystone II and Sitara AM5728 are used. To assure certification, the WCET constraints of the resulting near-optimal Pareto solutions are verified through formally validated bounding frameworks.

Mots clés: Heterogeneous multicore platforms; Task and memory mapping; Multi-objective optimization; DDR SDRAM

Domaines: Physique [physics]; Sciences de l'ingénieur [physics]

Alfonso Mascareñas González, Jean-Baptiste Chaudron, Frédéric Boniol, Youcef Bouchebaba, Jean-Loup Bussenot. Task and Memory Mapping Optimization for SDRAM Interference Minimization on Heterogeneous MPSoCs. 2022 IEEE 27th International Conference on Emerging Technologies and Factory Automation (ETFA), Sep 2022, Stuttgart, Germany. pp.0. ⟨hal-03940542⟩